Performance Analysis of Low Power Dissipation and High Speed Voltage Sense Amplifier

This CMOS voltage sense amplifier or comparator is designed by adding dual input single output differential amplifier which is added in place of back-to-back inverter in the latch stage. This method is used to completely remove the input noise present in the circuit. Using this dual input single output differential amplifier the analog-to-digital conversions with high speed, lower power dissipation and immune to noise can be achieved. The circuits are designed using 180nm Technology and CMOS at a power supply of 1.8 Volts in Cadence. This proposed single output differential amplifier is based on two cross coupled differential pairs with positive feedback and switchable current sources and having lower power dissipation, higher speed and it is shown to be very robust against transistor mismatch and is noise immunity. There is a reduction of 24% in the delay of the circuit and also the energy consumed in the circuit is only 77% of the previous circuit and hence there is an increase in speed and decrease in the dissipation of the circuit.